How ngxx-fus/riscvtutorial works
This repository is a RISC-V tutorial built around Chipyard: it contains configurable SoC generators, FPGA platform support, simulation integrations, and bare-metal examples. A typical user journey is selecting a configuration, generating a SoC, then running or deploying it; the examples demonstrate UART/GPIO access and a RoCC accelerator. The README provides only the project title, and several subsystems are represented here by their tree paths rather than inspected source, so uncertain internal wiring is omitted.
Main entry points: ChipTop.scala Chip top · config SoC configs · Generator.scala Generator stage · main.c RoCC example
Components 19
SoC generation
- Generator stage
generators/chipyard/src/main/scala/Generator.scala - SoC configs
generators/chipyard/src/main/scala/config - Subsystem
generators/chipyard/src/main/scala/Subsystem.scala - Digital top
generators/chipyard/src/main/scala/DigitalTop.scala - Chip top
generators/chipyard/src/main/scala/ChipTop.scala - Clocking config
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
Cores and accelerators
- Tile config
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala - RoCC config
generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala - Spike tile
generators/chipyard/src/main/scala/SpikeTile.scala - Spike simulator
generators/chipyard/src/main/resources/csrc/spiketile.cc
Platforms and simulation
- FPGA platforms
fpga/src/main/scala - Simulation harness
generators/chipyard/src/main/scala/harness/TestHarness.scala - FireSim bridges
generators/firechip/src/main/scala/BridgeBinders.scala
Bare-metal software
- GPIO example
fpga/sw/helloWorld/src/main.c - RoCC example
fpga/sw/rocc/src/main.c - RoCC instructions
fpga/sw/rocc/include/rocc.h
Other components
- SoC developer
- UART and GPIO
- RoCC accelerator
Connections 15
- SoC developer → Generator stage: selects configuration
- SoC configs → Generator stage: configures generation
- Generator stage → Chip top: generates design
- Subsystem → Digital top: composes subsystem
- Digital top → Chip top: forms chip top
- Clocking config → SoC configs: sets clock parameters
- Tile config → SoC configs: sets tile parameters
- RoCC config → SoC configs: assigns accelerators
- Spike tile → Spike simulator: exchanges simulation requests
- Chip top → Simulation harness: instantiated by
- Chip top → FPGA platforms: targets platform
- Chip top → FireSim bridges: uses simulation bridges
- GPIO example → UART and GPIO: accesses registers
- RoCC example → RoCC instructions: uses instruction macros
- RoCC example → RoCC accelerator: issues custom instruction