How lucas-farimart/arandu works
Arandu is a naive DNN accelerator implemented in RTL. Its documented focus is an SRAM subsystem that stores weights and activations while providing latency-hidden bandwidth. The tree also contains software and data-memory utilities for quantization, network-memory layout, and packing analysis. RTL excerpts were not supplied, so the hardware component relationships below are documented at subsystem level rather than asserted as source-verified calls; the evidence limit is noted with dashed links.
Main entry points: sram_subsystem.sv SRAM subsystem · arandu_core.sv Accelerator core · mem_generator.py Model memory export · neuron_int8.sv INT8 neuron
Components 28
Accelerator RTL
- Arandu top
rtl/arandu.sv - Accelerator core
rtl/arandu_core.sv - Control logic
rtl/arandu_ctrl.sv - FSM controller
rtl/fsm_controller.sv - INT8 NPU
rtl/npu_int8.sv - FP32 NPU
rtl/npu_fp32.sv - INT8 neuron
rtl/neuron_int8.sv - FP32 neuron
rtl/neuron_fp32.sv - Requantization
rtl/requant_unit.sv - Booth multiplier
rtl/booth_radix4.sv - FP32 adder
rtl/fp32_add.sv
On-chip Memory
- SRAM subsystem
rtl/sram_subsystem.sv - Activation SRAM
rtl/mem_actvs.sv - Weight SRAM
rtl/mem_weights.sv - Metadata map
rtl/metadata_map.sv - DRAM controller
rtl/dram_controller.sv - SRAM macro
rtl/sram_32x512_1rw.v
Model and Data Preparation
- TFLite quantization
software/quant_tflite.py - Model memory export
data_mem/mem_generator.py - Network memory map
data_mem/memory_mapping.py - Layer data generator
data_mem/gen_layer64.py
Layout Analysis
- Word packing study
data_mem/word_analisys.py - Memory comparison
data_mem/mem_analisys.py - Package comparison
software/pkg_analysis.py - Matrix behavior
software/matrix_analysis.py - Stack simulation
software/stack_analysis.py - TensorFlow stack simulation
software/tensorflow_stack.py
Other components
- Model developer
Connections 23
- Model developer → TFLite quantization: trains and quantizes
software/quant_tflite.py - Model developer → Model memory export: exports model
data_mem/mem_generator.py - Model developer → Network memory map: configures shape
data_mem/memory_mapping.py - Arandu top → Accelerator core: routes to
README.md - Accelerator core → Control logic: coordinates
- Accelerator core → INT8 NPU: dispatches
- Accelerator core → FP32 NPU: dispatches
- Control logic → FSM controller: controls
- INT8 NPU → INT8 neuron: computes with
- FP32 NPU → FP32 neuron: computes with
- INT8 neuron → Booth multiplier: multiplies with
- INT8 neuron → Requantization: requantizes with
- FP32 neuron → FP32 adder: adds with
- Accelerator core → SRAM subsystem: accesses
- SRAM subsystem → Activation SRAM: stores activations
- SRAM subsystem → Weight SRAM: stores weights
- SRAM subsystem → Metadata map: uses map
- SRAM subsystem → SRAM macro: uses macro
- SRAM subsystem → DRAM controller: interfaces with
- TFLite quantization → Model memory export: provides model weights
- Model memory export → Weight SRAM: prepares weight data
- Network memory map → Metadata map: describes dimensions
- Layer data generator → Model memory export: generates sample data