How lengqingsnow/cns2fpga works
CNS2FPGA is a research workflow for extracting connectome-constrained neural circuits, modeling and checking them, compiling fixed-point images, and validating execution on FPGA hardware. Its central user-to-result path runs from MaleCNS data through extraction, CPU references, compilation, RTL checks, and board measurements. Separate branches cover biological-plausibility analysis, courtship robustness, visual steering, baselines, and runtime image replacement. The README documents these stages; sampled source confirms selected runner dependencies, but not every subsystem’s internal wiring.
Main entry points: compile_hardware_ir.py Image compiler · 3_CPU Floating-Point Golden Model Float reference · run_experiment.py Courtship experiment · 15_Ethernet_Runtime_Deployment Ethernet image loading
Components 17
Circuit Extraction
- Circuit extraction
code/1_biological circuit - Subcircuit extraction
code/2_Subcircuit Automatic Extraction Tool/run_extractor.py
Modeling and Analysis
- Float reference
code/3_CPU Floating-Point Golden Model - Plausibility checks
code/4_Verify whether this model has basic biological plausibility - Fixed-point analysis
code/5_Fixed-Point Quantization Analysis/run_quantization_analysis.py
FPGA Implementation
- Image compiler
code/6_Connectome Compiler/compile_hardware_ir.py - FPGA architecture
code/7_Minimum FPGA Architecture - RTL co-simulation
code/8_RTL Bit-Exact Co-Simulation - Board validation host
code/9_KU115 FPGA Validation/host/step9_host.py
Runtime Deployment
- JTAG image loading
code/14_Runtime Reconfigurable Deployment - Ethernet image loading
code/15_Ethernet_Runtime_Deployment
Circuit Studies
- Courtship experiment
code/10_Complete Courtship-Song Circuit Experiment/run_experiment.py - Robustness study
code/11_Courtship-Song Robustness/run_robustness.py - Visual steering circuit
code/12_Visual-to-Steering Circuit - Baselines and ablations
code/13_Baselines and Ablations/run_baselines.py
Other components
- MaleCNS data
- AXKU115 board
Connections 21
- MaleCNS data → Circuit extraction: extracts from
- Circuit extraction → Subcircuit extraction: selects subgraphs
- Subcircuit extraction → Float reference: supplies circuit IR
- Float reference → Plausibility checks: evaluates model
- Float reference → Fixed-point analysis: compares precision
- Fixed-point analysis → Image compiler: selects format
- Subcircuit extraction → Image compiler: supplies graph IR
- Image compiler → FPGA architecture: generates images
- FPGA architecture → RTL co-simulation: checks RTL
- Image compiler → Board validation host: provides reference image
- Board validation host → AXKU115 board: prepares board trials
- AXKU115 board → Courtship experiment: provides captures
- Float reference → Courtship experiment: provides CPU reference
- Courtship experiment → Robustness study: supplies baseline
- Visual steering circuit → Baselines and ablations: supplies circuit
- Image compiler → JTAG image loading: loads compiled image
- JTAG image loading → AXKU115 board: configures at runtime
- Image compiler → Ethernet image loading: loads compiled image
- Ethernet image loading → AXKU115 board: uploads over UDP
- Visual steering circuit → Ethernet image loading: provides visual image
- Courtship experiment → Ethernet image loading: provides courtship image