How kubeworkz/grx930 works
GRX930 is a multi-core RISC-V SoC integrating two GEMM NPUs, coherent caching, an AXI4 fabric, memory, and peripherals. A typical workload is supplied as firmware or an ELF image, booted on a CPU, and configured through memory-mapped NPU registers; the NPU reads operands, computes GEMM, and writes results to memory for CPU-side use. The README supplies the system topology and major capabilities; sampled firmware and loader code support the software-side flow, but RTL implementation details were not sampled.
Main entry points: c930_axi_crossbar.sv AXI4 Crossbar · main.c Firmware Commands · c930_npu_core.sv GEMM Controller · c930_mmio_bridge.sv MMIO Bridge
Components 23
Software and CPUs
- Firmware Commands
c930/sw/firmware/main.c - ELF Loader
c930/sw/firmware/elf64_loader.c - NPU Driver
c930/sw/c930_npu_driver.c - RV64IMAC Cores
- I/D Caches
Interconnect and Cache
- AXI4 Crossbar
c930/rtl/c930_axi_crossbar.sv - Coherent L2
c930/rtl/c930_l2.sv - Cache Adapter
c930/rtl/c930_axi_cache_adapter.sv - DMA Arbiter
c930/rtl/c930_axi_dma_arb.sv
Neural Processing
- NPU Instances
c930/rtl/c930_npu_top.sv - NPU Registers
c930/rtl/c930_npu_csr.sv - GEMM Controller
c930/rtl/c930_npu_core.sv - Systolic Array
c930/rtl/c930_systolic_array.sv - Tensor Elements
c930/rtl/c930_tensor_pe.sv - Activation Unit
c930/rtl/c930_npu_act.sv - NPU DMA
c930/rtl/c930_npu_dma.sv
Memory and Peripherals
- MMIO Bridge
c930/rtl/c930_mmio_bridge.sv - UART
c930/rtl/c930_uart.sv - APLIC
c930/rtl/c930_aplic.sv - Boot ROM
c930/rtl/c930_bootrom.sv - DDR / BRAM
c930/rtl/c930_ddr.sv - DDR3L Controller
c930/rtl/c930_ddr3l.sv
Other components
- Host / User
Connections 24
- Host / User → Firmware Commands: supplies commands
- Host / User → ELF Loader: provides ELF
- Firmware Commands → ELF Loader: loads image
- Firmware Commands → NPU Driver: configures NPU
- Firmware Commands → RV64IMAC Cores: runs on
- RV64IMAC Cores → I/D Caches: uses
- I/D Caches → Cache Adapter: accesses memory
- Cache Adapter → AXI4 Crossbar: issues AXI
- AXI4 Crossbar → Coherent L2: routes requests
- AXI4 Crossbar → NPU Instances: routes requests
- AXI4 Crossbar → MMIO Bridge: routes MMIO
- NPU Instances → NPU Registers: exposes registers
- NPU Registers → GEMM Controller: starts jobs
- GEMM Controller → Systolic Array: controls GEMM
- Systolic Array → Tensor Elements: distributes operands
- GEMM Controller → Activation Unit: applies activation
- GEMM Controller → NPU DMA: requests transfers
- NPU DMA → DMA Arbiter: requests arbitration
- DMA Arbiter → AXI4 Crossbar: forwards DMA
- AXI4 Crossbar → DDR / BRAM: accesses memory
- AXI4 Crossbar → DDR3L Controller: routes memory traffic
- MMIO Bridge → UART: accesses registers
- MMIO Bridge → APLIC: accesses registers
- RV64IMAC Cores → Boot ROM: boots from