How kalikibhuvanesh/know-knowledge works
This is an FPGA power-governor implementation with a Vitis demo application. The documented workflow is to configure the memory-mapped registers, run workload and thermal scenarios, then read and print status. The file tree names the hardware controller, activity monitor, and register file, but their source and interconnections were not sampled; those links are therefore omitted.
Main entry points: pwrgov_main.c Demo application · pwrgov_top.v Governor top
Components 5
Software demo
- Demo application
pwrgov_main.c
FPGA hardware
- Governor top
pwrgov_top.v - FSM controller
fsm_controller.v - Activity monitor
activity_monitor.v - Register file
register_file.v
Connections 2
- Demo application → Governor top: writes configuration
- Governor top → Demo application: returns status