infineon/kitprog3

Purpose and deliverables

KitProg3 is embedded firmware for the PSoC5LP-based KitProg3 debug/programming probe. It builds with PSoC Creator 4.4 into HEX and Cypress bootloader (.cyacd) images; distribution and field updates are performed by the external fw-loader utility. The DAPLink codebase itself is explicitly external.

• KitProg3.cydsn/KitProg3.cyprj

• KitProg3.cydsn/KitProg3.cydwr

• KitProg3.cywrk

Firmware entry and system composition

The primary application starts in main.c and coordinates probe operation through hardware/device definitions, KitProg state, and generated PSoC peripheral code. The PSoC schematic is a material hardware boundary: it defines the board wiring and components consumed by the generated source.

• KitProg3.cydsn/main.c

• KitProg3.cydsn/kitprog.h

• KitProg3.cydsn/TopDesign/TopDesign.cysch

USB host interface and command boundary

USB is the host-facing control plane. The USB interface/user-HID layers receive host requests and bridge them into firmware command processing; generated USBFS vendor and endpoint ISR code sits below this boundary. Host protocol compatibility is therefore concentrated at the USB/command interfaces rather than in transport drivers.

• KitProg3.cydsn/usbinterface.c

• KitProg3.cydsn/usb_user_hid.c

• KitProg3.cydsn/commandprocessor.h

Debug-access protocol stack

The probe’s target-debug path supports CMSIS-DAP-facing logic plus SWD and JTAG data-port implementations. DAP configuration/vendor extensions adapt the standard debug protocol to KitProg behavior, while SWD/JTAG layers control physical target access.

• KitProg3.cydsn/DAP.c

• KitProg3.cydsn/SW_DP.c

• KitProg3.cydsn/JTAG_DP.c

Application modes and target bridges

Mode switching and bridge interfaces separate normal debug/provisioning functions from target-facing bridge behavior. The application switch is the likely control boundary for selecting probe functions, while bridge APIs isolate higher-level commands from concrete target transports.

• KitProg3.cydsn/app_switch.c

• KitProg3.cydsn/bridgesInterface.c

• KitProg3.cydsn/swd.c

Hardware control and concurrency

Power, LEDs, reset-related ISR logic, and mutexes manage board-visible state and timing-sensitive access. These components operate below command/protocol layers and must preserve electrical and synchronization constraints when target transactions occur.

• KitProg3.cydsn/power.c

• KitProg3.cydsn/led.c

• KitProg3.cydsn/mutex.c

Boot and deployment boundaries

A separate PSoC bootloader project provides the firmware-update runtime; the main application emits the update artifact it consumes. Windows driver packages provide host enumeration/support for KitProg-family USB and UART devices, but are not firmware runtime code.

• KitProg3_Bootloader.cydsn/main.c

• KitProg3_Bootloader.cydsn/KitProg3_Bootloader.cyprj

• drivers/KitProg3/KitProg3/Win7/KitProg3.inf

Shared component infrastructure

The repository also contains a reusable PSoC Creator SPI Master component/library, including generated embedded C API and Creator-side customizer code. It is design-time component infrastructure, distinct from the probe application and bootloader projects.

• KitProg3_Library.cylib/SPI_Master_v2_50/API/SPI_Master.c

• KitProg3_Library.cylib/SPI_Master_v2_50/SPI_Master_v2_50.cysch