ichen522/axi_dma

How ichen522/axi_dma works

This repository implements a four-channel AXI DMA: software programs transfers through AXI4-Lite, the DMA arbitrates and moves data over AXI4, and software observes completion or error interrupts. The RTL also includes byte realignment, burst management, error handling, and parameterized outstanding reads. Separate branches capture the documented verification, arbiter fairness proof, implementation sign-off, and bandwidth/area analysis capabilities. RTL relationships follow the README’s architecture and transfer descriptions; unsampled verification and implementation internals are represented only at their supported directory paths.

Main entry points: dma_top.sv DMA Top · dma_engine.sv Shared Engine · dma_csr.sv CSR and IRQ · dma_channel.sv Channel Control

Components 16

Control RTL

DMA Top rtl/dma_top.sv
CSR and IRQ rtl/dma_csr.sv
Channel Control rtl/dma_channel.sv

AXI Datapath

Shared Engine rtl/dma_engine.sv
Round-Robin Arbiter rtl/dma_rr_arb.sv
Descriptor and W FIFOs rtl/dma_fifo.sv

Verification

Simulation Testbench tb
C Reference Model tb/ref/dma_ref.c
Fairness Proof formal/arb_fairness.sv
Mutation Checks scripts/mutants.py

Implementation

Synthesis and STA syn

Performance Analysis

Area Sweep analysis/area_sweep.sh
Utilisation Sweep analysis/sweep.py
Area Trade-off analysis/area_tradeoff.py

Other components

Software
AXI Memory

Connections 21

Software → CSR and IRQ: programs via AXI-Lite README.md
CSR and IRQ → Software: signals IRQ README.md
DMA Top → CSR and IRQ: instantiates README.md
DMA Top → Channel Control: instantiates README.md
DMA Top → Shared Engine: instantiates README.md
CSR and IRQ → Channel Control: sends start and config README.md
Channel Control → CSR and IRQ: reports done or error README.md
Channel Control → Shared Engine: requests chunks README.md
Shared Engine → Round-Robin Arbiter: arbitrates requests README.md
Shared Engine → Descriptor and W FIFOs: uses queues README.md
Shared Engine → AXI Memory: issues AXI bursts README.md
AXI Memory → Shared Engine: returns read and write responses README.md
Simulation Testbench → DMA Top: simulates RTL README.md
Simulation Testbench → C Reference Model: checks against README.md
Fairness Proof → Round-Robin Arbiter: proves fairness README.md
Mutation Checks → Simulation Testbench: checks bug detection README.md
DMA Top → Synthesis and STA: implemented and timed README.md
Area Sweep → Synthesis and STA: measures configurations
Utilisation Sweep → DMA Top: simulates configurations analysis/sweep.py
Area Trade-off → Utilisation Sweep: joins utilisation data analysis/area_tradeoff.py
Area Trade-off → Area Sweep: joins area data analysis/area_tradeoff.py

Drawn by GitDiagram on November 11, 2026 from the repository's file tree, README and source files. Read as Markdown ·