How haroonhaider4414-create/mips-single-cycle-cpu works
This repository is named as a MIPS single-cycle CPU, with Verilog files for control, datapath operations, registers, and instruction/data memory. The README provides no workflow details, and no source excerpts are available, so the graph groups components by their apparent roles but does not assert connections or execution order.
Components 15
Control
- Main control
MainCon.v - ALU control
ALUcon.v
Datapath
- ALU
ALu.v - AND unit
And.v - Mux 1
Mux1.v - Mux 2
Mux2.v - Mux 3
Mux3.v - Mux 4
Mux4.v - Program counter
PC.v - Sign extend
SignExtend.v - Shift left 2
ShitLeft2.v
Storage
- Register file
RegFile.v - Instruction memory
instMem.v - Data memory
Datamem.v
Other components
- CPU top
MipsCPU