How galdv/cpucamp works
This repository is a Hack CPU FPGA challenge bundle: it includes a sample assembly program, assembled machine code, a converter to Intel HEX, and the documented target-system design. The user workflow is to assemble Hack code, convert it, program the FPGA, and observe execution and runtime. The tree contains no Verilog source, so hardware details below reflect README documentation, not inspected RTL; the converter is the only sampled implementation.
Main entry points: CPU_Garage.qar Hack CPU · hack_to_hex.py Hack to HEX · rom.hack Hack machine code · rom.hex Intel HEX image
Components 13
Program artifacts
- Sample assembly
asm/rom.asm - Hack machine code
hack/rom.hack
Image conversion
- Hack to HEX
python/hack_to_hex.py - Intel HEX image
hex/rom.hex
Documented FPGA system
- Hack CPU
CPU_Garage.qar - Instruction ROM
CPU_Garage.qar - Data RAM
CPU_Garage.qar - VGA memory view
CPU_Garage.qar - Performance counter
CPU_Garage.qar - Seven-segment display
CPU_Garage.qar
Other components
- Nand2Tetris assembler
- FPGA programmer
- Execution viewer
Connections 10
- Nand2Tetris assembler → Hack machine code: assembles
README.md - Hack to HEX → Hack machine code: reads
python/hack_to_hex.py - Hack to HEX → Intel HEX image: writes
python/hack_to_hex.py - FPGA programmer → Instruction ROM: programs
README.md - Instruction ROM → Hack CPU: supplies instructions
README.md - Hack CPU → Data RAM: reads and writes
README.md - Data RAM → VGA memory view: provides display data
README.md - Hack CPU → Performance counter: execution is timed
README.md - Performance counter → Seven-segment display: drives runtime display
README.md - VGA memory view → Execution viewer: displays memory
README.md