# devaharsha28/t808 architecture

> Architecture diagram of the GitHub repository devaharsha28/t808, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-25). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/devaharsha28/t808
- Repository: https://github.com/devaharsha28/t808

## Overview

T808 is a Verilog implementation of a small 16-bit-instruction CPU, intended to run programs loaded from a hex file. The documented workflow is to place instructions in the ROM image and start execution at address 00; the example demonstrates accumulator arithmetic. The RTL tree identifies the CPU, ALU, accumulator, program counter, RAM, and ROM modules. Source excerpts were unavailable, so internal module-to-module wiring beyond documented ROM loading and execution is not asserted.

Main entry points: [`programs/program.hex`](https://github.com/devaharsha28/t808/blob/main/programs/program.hex) (Hex program), [`rtl/rom.v`](https://github.com/devaharsha28/t808/blob/main/rtl/rom.v) (ROM), [`rtl/cpu.v`](https://github.com/devaharsha28/t808/blob/main/rtl/cpu.v) (CPU)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_program["Program input"]
  node_image["Hex program<br/>[program.hex]"]
end

subgraph group_core["CPU core"]
  node_cpu["CPU<br/>[cpu.v]"]
  node_alu["ALU<br/>[alu.v]"]
  node_acc["Accumulator<br/>[acc.v]"]
  node_pc["Program counter<br/>[pc.v]"]
end

subgraph group_memory["Memory"]
  node_rom["ROM<br/>[rom.v]"]
  node_ram["RAM<br/>[ram.v]"]
end

node_user(("Program author"))

node_user -->|"edits"| node_image
node_image -->|"loads instructions"| node_rom
node_cpu -->|"executes from"| node_rom

click node_image "https://github.com/devaharsha28/t808/blob/main/programs/program.hex"
click node_cpu "https://github.com/devaharsha28/t808/blob/main/rtl/cpu.v"
click node_alu "https://github.com/devaharsha28/t808/blob/main/rtl/alu.v"
click node_acc "https://github.com/devaharsha28/t808/blob/main/rtl/acc.v"
click node_pc "https://github.com/devaharsha28/t808/blob/main/rtl/pc.v"
click node_rom "https://github.com/devaharsha28/t808/blob/main/rtl/rom.v"
click node_ram "https://github.com/devaharsha28/t808/blob/main/rtl/ram.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_image toneBlue
class node_cpu,node_alu,node_acc,node_pc toneAmber
class node_rom,node_ram toneMint
class node_user toneIndigo
```

## Components

### Program input

- [Hex program](https://github.com/devaharsha28/t808/blob/main/programs/program.hex): `programs/program.hex`

### CPU core

- [CPU](https://github.com/devaharsha28/t808/blob/main/rtl/cpu.v): `rtl/cpu.v`
- [ALU](https://github.com/devaharsha28/t808/blob/main/rtl/alu.v): `rtl/alu.v`
- [Accumulator](https://github.com/devaharsha28/t808/blob/main/rtl/acc.v): `rtl/acc.v`
- [Program counter](https://github.com/devaharsha28/t808/blob/main/rtl/pc.v): `rtl/pc.v`

### Memory

- [ROM](https://github.com/devaharsha28/t808/blob/main/rtl/rom.v): `rtl/rom.v`
- [RAM](https://github.com/devaharsha28/t808/blob/main/rtl/ram.v): `rtl/ram.v`

### Other components

- **Program author**

## Connections

- Program author → Hex program: edits
- Hex program → ROM: loads instructions
- CPU → ROM: executes from