How cmu-safari/mqsim works
MQSim simulates SSD I/O from configured workloads through host protocols and device firmware to flash storage, with end-to-end timing and statistics. The README documents NVMe and SATA, synthetic or trace-based flows, caching, address-mapping options, transaction scheduling, and garbage collection/wear leveling. The sampled code confirms configuration and workload parsing, discrete-event scheduling, cache-to-FTL dispatch, and block allocation; some other subsystem connections below reflect documented product behavior rather than inspected implementation. Similar implementations are grouped by responsibility.
Main entry points: IO_Flow_Base.cpp I/O flows · FTL.cpp Flash translation layer · main.cpp Program entry · Execution_Parameter_Set.h Execution settings
Components 21
Inputs and host
- Execution settings
src/exec/Execution_Parameter_Set.h - Workload settings
src/exec/IO_Flow_Parameter_Set.h - I/O flows
src/host/IO_Flow_Base.cpp - Synthetic and trace flows
src/host/IO_Flow_Synthetic.cpp - PCIe and SATA host
src/host/PCIe_Root_Complex.cpp
SSD device
- NVMe and SATA interfaces
src/ssd/Host_Interface_Base.cpp - SSD device
src/exec/SSD_Device.cpp
Firmware and policies
- DRAM data cache
src/ssd/Data_Cache_Manager_Base.h - NVM firmware
src/ssd/NVM_Firmware.cpp - Flash translation layer
src/ssd/FTL.cpp - Address mapping
src/ssd/Address_Mapping_Unit_Base.cpp - Transaction scheduler
src/ssd/TSU_Base.cpp - GC and wear leveling
src/ssd/GC_and_WL_Unit_Base.cpp
Flash media
- Flash block manager
src/ssd/Flash_Block_Manager.cpp - ONFI channel
src/ssd/ONFI_Channel_Base.cpp - NVM PHY
src/ssd/NVM_PHY_Base.cpp - Flash chip and arrays
src/nvm_chip/flash_memory/Flash_Chip.cpp
Simulation and results
- Program entry
src/main.cpp - Event engine
src/sim/Engine.cpp - Statistics
src/ssd/Stats.cpp
Other components
- User
Connections 22
- User → Program entry: runs
- User → Execution settings: provides
- User → Workload settings: provides
- Program entry → Execution settings: parses
- Program entry → Workload settings: reads
- Workload settings → Synthetic and trace flows: defines flows
- Synthetic and trace flows → I/O flows: configures
- I/O flows → PCIe and SATA host: sends I/O
- PCIe and SATA host → NVMe and SATA interfaces: transfers requests
- NVMe and SATA interfaces → DRAM data cache: services I/O
- DRAM data cache → Flash translation layer: dispatches transactions
- Flash translation layer → Address mapping: translates addresses
- Flash translation layer → Transaction scheduler: schedules transactions
- Address mapping → Flash block manager: allocates pages
- Transaction scheduler → ONFI channel: issues transactions
- GC and wear leveling → Flash block manager: requests block operations
- Flash block manager → ONFI channel: provides page addresses
- ONFI channel → NVM PHY: transfers commands
- NVM PHY → Flash chip and arrays: operates flash
- Event engine → Event engine: dispatches events
- I/O flows → Statistics: records response times
- Execution settings → SSD device: configures device