# bhavesh270106/ahb_to_apb-bridge-design architecture

> Architecture diagram of the GitHub repository bhavesh270106/ahb_to_apb-bridge-design, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-06-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/bhavesh270106/ahb_to_apb-bridge-design
- Repository: https://github.com/bhavesh270106/ahb_to_apb-bridge-design

## Overview

1. **Repository purpose**
   - This repo implements a synthesizable **AHB-to-APB bridge** in Verilog.
   - The goal is to translate a single AHB read/write transaction into the two-cycle APB protocol, while keeping address, control, and data aligned across the bridge.

2. **Top-level structure**
   - `bridge_top.v` is the integration point for the design.
   - The project is organized around one real hardware block, the bridge, plus surrounding stimulus modules used to exercise it in simulation and validation.

3. **Core bridge boundary**
   - The only synthesizable subsystem is the bridge itself.
   - The other Verilog files serve as protocol-side endpoints for testing:
     - `AHB_Master.v` generates AHB master transactions.
     - `AHB_Slave_Interface.v` models the AHB-side slave-facing behavior.
     - `APB_Interface.v` models the APB peripheral-side behavior.
   - This means the repo is primarily a **bus-interface RTL design with testbench wrappers**, not a full SoC.

4. **Functional decomposition**
   - `APB_Controller.v` appears to be the control/state-machine block.
   - It is responsible for sequencing the APB transfer phases and generating bridge control outputs such as select and enable timing.
   - `AHB_Slave_Interface.v` likely handles the AHB-side handshake and captures the incoming address/control phase from the master side.
   - `APB_Interface.v` likely drives the APB-side outputs and returns read data to the AHB side.

5. **Main data flow**
   - On an AHB write:
     - The master presents address, write control, and write data.
     - The bridge latches the address/control, decodes the target peripheral, and drives APB address, select, enable, and write data.
   - On an AHB read:
     - The bridge captures the AHB request, issues the APB read, then returns APB read data back onto the AHB read path.
   - The bridge therefore acts as a **protocol converter and timing adapter** between the two buses.

6. **Control and timing flow**
   - AHB is treated as the initiating, higher-performance side with master-driven address/control phases.
   - APB is treated as the lower-complexity destination side that always uses a setup phase followed by an enable phase.
   - The bridge inserts this APB timing by generating `PSELx` and `PENABLE`, while holding the APB address stable for the full transfer.

7. **Address decode and peripheral selection**
   - The readme states the bridge decodes the address to generate `PSELx`.
   - Only one APB select is active per transfer, so the bridge likely contains combinational address-decoding logic plus a registered control path to preserve stability during the APB transaction.

8. **Handshake and response behavior**
   - The AHB side uses `HREADY` and `HRESP` to indicate completion and status.
   - The APB side relies on `PSELx`, `PENABLE`, and the read/write direction signal rather than multi-response handshaking.
   - The bridge’s job is to convert the AHB transaction into the APB timing model and return completion at the appropriate point.

9. **Simulation/test setup**
   - The repo is validated with a **single read and single write** sequence.
   - `AHB_Master.v` and `APB_Interface.v` are used to generate and observe bus activity, while the bridge under test converts the transaction between protocols.
   - The README explicitly notes that burst support and arbitration are not implemented yet.

10. **Tooling and implementation context**
   - The design is written in **Verilog**.
   - It was simulated in **ModelSim** and synthesized in **Quartus Prime** for a **Cyclone V** FPGA target.
   - Those tools matter architecturally because the bridge is intended to be both simulation-valid and synthesis-ready, unlike the surrounding test modules.

11. **System-level architectural role**
   - In AMBA terms, this repository implements the classic boundary between a fast system bus and a simpler peripheral bus.
   - The bridge is the only subsystem that must understand both protocols and enforce their timing differences; all other modules exist to stimulate or observe that conversion.

12. **Current scope and limitations**
   - Supported: single AHB read, single AHB write, APB address decode, APB select generation, and APB enable sequencing.
   - Not supported yet: bursts, arbitration, or broader multi-master behavior.
   - For an architecture diagram, the key boundary is a **single master-side AHB interface feeding a bridge FSM, which outputs APB-side control/data to a peripheral interface**.

Main entry points: [`APB_Interface.v`](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Interface.v) (APB Side), [`APB_Controller.v`](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Controller.v) (APB FSM), [`bridge_top.v`](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/bridge_top.v) (Top), [`AHB_Slave_Interface.v`](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/AHB_Slave_Interface.v) (AHB Side)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_core["Bridge RTL"]
  node_bridge_top["Top<br/>integration<br/>[bridge_top.v]"]
  node_ahb_slave["AHB Side<br/>ahb slave iface"]
  node_apb_ctrl["APB FSM<br/>apb control<br/>[APB_Controller.v]"]
  node_apb_iface["APB Side<br/>apb iface<br/>[APB_Interface.v]"]
end

subgraph group_tb["Validation"]
  node_ahb_master["AHB Master<br/>stimulus<br/>[AHB_Master.v]"]
  node_apb_model["APB Model<br/>peripheral model<br/>[APB_Interface.v]"]
end

node_ahb_master -->|"AHB requests"| node_bridge_top
node_bridge_top -->|"capture"| node_ahb_slave
node_ahb_slave -->|"txn state"| node_apb_ctrl
node_apb_ctrl -->|"phase control"| node_apb_iface
node_apb_ctrl -->|"HREADY/HRESP"| node_bridge_top
node_apb_iface -->|"APB bus"| node_apb_model
node_apb_model -->|"read data"| node_apb_iface
node_apb_iface -->|"rdata path"| node_ahb_slave

click node_bridge_top "https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/bridge_top.v"
click node_ahb_slave "https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/AHB_Slave_Interface.v"
click node_apb_ctrl "https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Controller.v"
click node_apb_iface "https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Interface.v"
click node_ahb_master "https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/AHB_Master.v"
click node_apb_model "https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Interface.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_bridge_top,node_ahb_slave,node_apb_ctrl,node_apb_iface toneBlue
class node_ahb_master,node_apb_model toneAmber
```

## Components

### Bridge RTL

Synthesizable AHB-to-APB bridge logic and top-level integration.

- [Top](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/bridge_top.v): integration · Top-level integration point that wires the bridge and its bus-side endpoints. · `bridge_top.v`
- [AHB Side](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/AHB_Slave_Interface.v): ahb slave iface · Captures AHB address/control, handshake, and completion behavior on the slave-facing side of the bridge. · `AHB_Slave_Interface.v`
- [APB FSM](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Controller.v): apb control · Sequencer/state machine that generates APB setup and enable timing and coordinates transfer progress. · `APB_Controller.v`
- [APB Side](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Interface.v): apb iface · Drives APB address, select, enable, write data, and read-data return behavior. · `APB_Interface.v`

### Validation

Simulation-side masters and peripheral-side models used to exercise the bridge.

- [AHB Master](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/AHB_Master.v): stimulus · Testbench master that issues single read and write transactions into the bridge. · `AHB_Master.v`
- [APB Model](https://github.com/bhavesh270106/ahb_to_apb-bridge-design/blob/main/APB_Interface.v): peripheral model · Peripheral-side endpoint used to observe APB activity and complete simulated transfers. · `APB_Interface.v`

## Connections

- AHB Master → Top: AHB requests · Generates read/write transactions into the bridge top-level.
- Top → AHB Side: capture · Routes incoming AHB address, control, and handshake signals into the AHB-side interface.
- AHB Side → APB FSM: txn state · Transfers the latched transaction context into the APB control path.
- APB FSM → APB Side: phase control · Drives APB setup/enable sequencing and transfer timing.
- APB FSM → Top: HREADY/HRESP · Returns completion and response status to the AHB side.
- APB Side → APB Model: APB bus · Presents APB address, select, enable, and write data to the peripheral-side model.
- APB Model → APB Side: read data · Supplies APB read-back data for return to the bridge.
- APB Side → AHB Side: rdata path · Feeds APB read data back toward the AHB-side response path.