How anoor3/argus works
ARGUS is an FPGA-based hardware validation instrument with host software for running repeatable test plans and reviewing captured results. The principal workflow is a user launching a plan, the host issuing register commands over a transport, and the instrument observing or stimulating the DUT while recording timestamped events. The tree shows distinct control, capture, stimulus, and safety subsystems. Host-side calls are supported by sampled source; RTL relationships are kept conservative because RTL implementation excerpts were not provided.
Main entry points: cli.py Host CLI · client.py Register client · plan.py Plan runner · report.py Plan reporting
Components 26
Host automation
- Host CLI
host/argus/cli.py - Plan runner
host/argus/plan.py - Register client
host/argus/client.py - Frame protocol
host/argus/protocol.py - Serial transport
- Mock instrument
host/argus/mock.py - Plan reporting
host/argus/report.py - Trace decoder
host/argus/trace.py - Timeline plotting
host/argus/plot.py
Instrument control
- ARGUS FPGA
rtl/argus_core.sv - Command router
rtl/command_router.sv - Register bank
rtl/csr_bank.sv - Test sequencer
rtl/test_sequencer.sv - Trigger engine
rtl/trigger_engine.sv
DUT interaction
- DUT monitors
rtl/gpio_monitor.sv - Serial stimulus
rtl/i2c_master.sv - SPI stimulus
rtl/spi_master.sv - ADC bridge
rtl/adc_bridge.sv
Event capture
- Timebase
rtl/timebase.sv - Capture subsystem
rtl/capture_subsystem.sv - Event logger
rtl/event_logger.sv - Trace buffer
rtl/trace_buffer.sv
Safety
- Fault controller
rtl/fault_controller.sv - Safety interlock
rtl/safety_interlock.sv
Other components
- Engineer
- Device under test
Connections 22
- Engineer → Host CLI: runs plan
- Host CLI → Plan runner: runs steps
- Host CLI → Register client: creates
- Host CLI → Plan reporting: formats results
- Host CLI → Serial transport: opens serial
- Host CLI → Mock instrument: selects mock
- Plan runner → Register client: issues register ops
- Register client → Frame protocol: encodes commands
- Register client → Serial transport: reads and writes
- Register client → Trace decoder: decodes records
- Plan reporting → Timeline plotting: exports timeline
- Serial transport → Command router: sends frames
- Command router → Register bank: routes register access
- Device under test → DUT monitors: signals
- Serial stimulus → Device under test: drives bus
- SPI stimulus → Device under test: drives bus
- ADC bridge → Device under test: interfaces signals
- DUT monitors → Capture subsystem: provides events
- Trigger engine → Capture subsystem: triggers capture
- Timebase → Event logger: timestamps events
- Event logger → Trace buffer: records events
- Fault controller → Safety interlock: signals faults