How anill-15/mac-unit works
This repository describes a Verilog MAC unit: operands are multiplied, the product is added to the prior accumulated value, and the updated value is retained for subsequent operations. The README identifies the multiplier, adder, accumulator register, clock, reset, and control logic as product components. Source excerpts were unavailable, so the graph reflects documented behavior only; it does not infer how the other Verilog files are wired.
Main entry points: mac_top.v Accumulator register
Components 7
MAC datapath
- MAC unit
mac_top.v - Multiplier
mac_top.v - Adder
mac_top.v - Accumulator register
mac_top.v
Other components
- Input operands
- Accumulated result
- Clock and reset
Connections 7
- Input operands → MAC unit: supplies operands
- MAC unit → Multiplier: dispatches multiply
- Multiplier → Adder: provides product
- Accumulator register → Adder: provides prior value
- Adder → Accumulator register: stores sum
- Accumulator register → Accumulated result: exposes value
- Clock and reset → MAC unit: controls operation