# abhik-ece/4-bit-alu-rtl-to-gdsii architecture
> Architecture diagram of the GitHub repository abhik-ece/4-bit-alu-rtl-to-gdsii, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-12). It is an AI-made overview: check details against the source.
- Interactive diagram: https://gitdiagram.com/abhik-ece/4-bit-alu-rtl-to-gdsii
- Repository: https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii
## Overview
This repository describes a 4-bit combinational ALU and its RTL-to-GDSII implementation. The principal workflow starts with the Verilog design, verifies its eight operations, synthesizes a gate-level netlist, and proceeds through physical-design stages to a final layout. The graph also includes the documented design constraints and physical-design results. No source excerpts were provided, so relationships are based on the README’s workflow descriptions; physical-stage implementation details are not independently verified.
Main entry points: [`rtl/alu.v`](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/rtl/alu.v) (4-bit ALU RTL), [`reports/nangate45/alu/base`](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base) (Cell Placement), [`synth`](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/synth) (Yosys Synthesis), [`synth/alu_netlist.v`](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/synth/alu_netlist.v) (Gate-level Netlist)
## Diagram (Mermaid)
```mermaid
flowchart TD
subgraph group_design["ALU Design"]
node_rtl["4-bit ALU RTL
[alu.v]"]
node_constraints["Timing Constraints
[constraint.sdc]"]
end
subgraph group_verification["Functional Verification"]
node_testbench["ALU Testbench
[alu_tb.v]"]
end
subgraph group_synthesis["Logic Synthesis"]
node_synthesis["Yosys Synthesis"]
node_netlist["Gate-level Netlist
[alu_netlist.v]"]
end
subgraph group_physical["Physical Implementation"]
node_floorplan["Floorplanning"]
node_power["Power Planning"]
node_placement["Cell Placement"]
node_cts["Clock Tree Stage"]
node_global_route["Global Routing"]
node_detailed_route["Detailed Routing"]
node_gds["Final GDSII
[6_final.gds]"]
node_reports["Physical Reports"]
end
node_designer(("Design Inputs"))
node_layout_viewer["KLayout"]
node_designer -->|"specifies"| node_rtl
node_rtl -->|"verifies"| node_testbench
node_rtl -->|"synthesizes"| node_synthesis
node_synthesis -->|"generates"| node_netlist
node_netlist -->|"implements"| node_floorplan
node_constraints -.->|"constrains"| node_floorplan
node_floorplan -->|"continues to"| node_power
node_power -->|"continues to"| node_placement
node_placement -->|"continues to"| node_cts
node_cts -->|"continues to"| node_global_route
node_global_route -->|"continues to"| node_detailed_route
node_detailed_route -->|"generates"| node_gds
node_gds -->|"inspected with"| node_layout_viewer
node_placement -->|"reports results"| node_reports
node_global_route -->|"reports results"| node_reports
node_detailed_route -->|"reports results"| node_reports
click node_rtl "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/rtl/alu.v"
click node_constraints "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/constraint.sdc"
click node_testbench "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/tb/alu_tb.v"
click node_synthesis "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/synth"
click node_netlist "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/synth/alu_netlist.v"
click node_floorplan "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
click node_power "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
click node_placement "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
click node_cts "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
click node_global_route "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
click node_detailed_route "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
click node_gds "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/results/nangate45/alu/base/6_final.gds"
click node_reports "https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base"
classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_rtl,node_constraints toneBlue
class node_testbench toneAmber
class node_synthesis,node_netlist toneMint
class node_floorplan,node_power,node_placement,node_cts,node_global_route,node_detailed_route,node_gds,node_reports toneRose
class node_designer,node_layout_viewer toneIndigo
```
## Components
### ALU Design
- [4-bit ALU RTL](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/rtl/alu.v): `rtl/alu.v`
- [Timing Constraints](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/constraint.sdc): `constraint.sdc`
### Functional Verification
- [ALU Testbench](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/tb/alu_tb.v): `tb/alu_tb.v`
### Logic Synthesis
- [Yosys Synthesis](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/synth): `synth`
- [Gate-level Netlist](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/synth/alu_netlist.v): `synth/alu_netlist.v`
### Physical Implementation
- [Floorplanning](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
- [Power Planning](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
- [Cell Placement](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
- [Clock Tree Stage](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
- [Global Routing](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
- [Detailed Routing](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
- [Final GDSII](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/blob/main/results/nangate45/alu/base/6_final.gds): `results/nangate45/alu/base/6_final.gds`
- [Physical Reports](https://github.com/abhik-ece/4-bit-alu-rtl-to-gdsii/tree/main/reports/nangate45/alu/base): `reports/nangate45/alu/base`
### Other components
- **Design Inputs**
- **KLayout**
## Connections
- Design Inputs → 4-bit ALU RTL: specifies (evidence: `README.md`)
- 4-bit ALU RTL → ALU Testbench: verifies (evidence: `README.md`)
- 4-bit ALU RTL → Yosys Synthesis: synthesizes (evidence: `README.md`)
- Yosys Synthesis → Gate-level Netlist: generates (evidence: `README.md`)
- Gate-level Netlist → Floorplanning: implements (evidence: `README.md`)
- Timing Constraints → Floorplanning: constrains
- Floorplanning → Power Planning: continues to (evidence: `README.md`)
- Power Planning → Cell Placement: continues to (evidence: `README.md`)
- Cell Placement → Clock Tree Stage: continues to (evidence: `README.md`)
- Clock Tree Stage → Global Routing: continues to (evidence: `README.md`)
- Global Routing → Detailed Routing: continues to (evidence: `README.md`)
- Detailed Routing → Final GDSII: generates (evidence: `README.md`)
- Final GDSII → KLayout: inspected with (evidence: `README.md`)
- Cell Placement → Physical Reports: reports results (evidence: `README.md`)
- Global Routing → Physical Reports: reports results (evidence: `README.md`)
- Detailed Routing → Physical Reports: reports results (evidence: `README.md`)